>300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology
We have fabricated 300 mm SiGe-On-Insulator substrates with the SmartCut approach. The donor wafers consisted in polished, 5 µm thick SiGe Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / SiGe) bilayers and (low Ge content SiGe / SiGe / low Ge content SiGe / SiGe) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the SiGe / low Ge content SiGe interfaces. After H ion implantation, bonding and splitting, a SC1 solution was used to etch the SiGe layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the SiGe layers. We obtained in the end 57 nm thick, flat SiGe layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).
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